SSTART=00, INSRC=0, SSTOP=00
Shifter Configuration N Register
SSTART | Shifter Start bit 0 (00): Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable 1 (01): Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift 2 (10): Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0 3 (11): Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1 |
SSTOP | Shifter Stop bit 0 (00): Stop bit disabled for transmitter/receiver/match store 1 (01): Reserved for transmitter/receiver/match store 2 (10): Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0 3 (11): Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1 |
INSRC | Input Source 0 (0): Pin 1 (1): Shifter N+1 Output |
PWIDTH | Parallel Width |